With advances of semiconductor technology into the nano scale, it is common to scale down the power supply voltage to match the power domain requirements of the scaled down transistors. For example, many core logic chips are now configured to operate at sub-one volt power supply voltage. However, many peripheral sub-systems like input/output (I/O) and memory chips may be configured to operate at higher power supply voltages. System-on-chip (SOC) designs typically include multiple power domains to power multiple core logic chips and sub-systems integrated on a single chip. A level shifter circuit is configured to interface between two power domains having different voltage and power characteristics. A voltage level shifter circuit typically converts a digital signal from one logic standard to another.
Traditional voltage level circuits may not operate properly in low input voltage applications since the low input voltage may be insufficient to change the latched state of the level shifter. Attempts to lower the threshold voltage of the input transistor may result in reduced reliability of the drain node of the input transistor since the transistor may not withstand a large voltage difference applied between its drain and other nodes.
From the foregoing discussion, it is desirable to provide tools and techniques to improve performance, reliability and lower cost of a voltage level shifter configured to handle very low input voltages.